The present invention relates to a charge storage capacitor for use in a dRAM (dynamic random access memory) which is small and yet has a large capacity as well as to a method for producing the same.
There has been realized a four-fold increase in the integration density of dRAMs in three years. The mainstream products have already been expanded from 64 k-bit dRAMs to 256 k-bit dRAMs, and mass production of 1 mega-bit dRAMs has already been started. The high integration has been attained by realization of reduction in the cell size which is known as "scaling rule". However, as a result of the reduction in the individual memory cell size, the storage capacity associated therewith also decreases, and this gives rise to serious problems such as a lowering in the S/N ratio and charge depletion due to alpha particles, which results in degradation of the reliability. In these circumstances, the following novel capacitor cells have been proposed with a view to increasing the storage capacity and are expected to replace the conventional planar capacitors, that is, a trench capacitor cell that utilizes the side walls of a trench provided in a substrate and a stacked capacitor cell in which the capacitance portion is defined by a stacked capacitor, the stacked capacitor cell being discussed in the literature titled "Novel high density, Stacked capacitor MOS RAM" in IEEE Int, Electron Devices Meeting Tech, Dig., pp. 348-351, Dec. (1978) by Koyanagi, Sumami, Hashimoto and Ashikawa. Among the novel capacitors, the latter, i.e., the stacked capacitor, has attracted attention as being a capacitor which is capable of coping with future demands for smaller devices, since, unlike the trench capacitor, the stacked capacitor needs no high degree of technique to provide a minute trench in a substrate.
Referring to FIG. 1, which is a sectional view of a dRAM having a conventional stacked capacitor, a process for producing the dRAM will be briefly explained below.
First, an oxide film 32 is grown on the surface of a single crystal substrate 31 to isolate elements from each other. Then, an oxide film 33 which is to define a gate oxide of a transistor is grown. A polycrystalline silicon 34 which contains an impurity is deposited to form a gate electrode. After the polycrystalline silicon 34 has been processed, a source 35 and a drain 36 are formed self-alignedly by ion implantation or other similar means. Next, in order to form a charge storage capacitor portion, a polycrystalline silicon 38 which contains an impurity is deposited on a region over the drain 36 as shown in FIG. 1. At this time, the polycrystalline silicon 38 is formed such as to extend over the gate electrode 34 and the field oxide 32 and therefore it is possible to increase the area of the capacitor in comparison with the conventional planar capacitor structure that utilizes only the plane of the substrate. It should be noted that the gate electrode 34 is covered with an insulating film 37 such as an oxide film. An oxide film 39 is formed over the polycrystalline silicon 38 formed as described above to define a dielectric film of the capacitor. A conductor 310 is deposited over the oxide film 39 to complete the capacitor. Further, an interlayer insulating film 311 is deposited over the conductor 310, and after a contact hole 312 has been opened in the insulating film 311 so that the source region 35 of the transistor is exposed, a conductor layer 313 which is to define a data line is formed.
Thus, the dRAM cell having a stacked capacitor has the advantage that it is possible to increase the storage capacity as compared with a planar dRAM cell in which a capacitor is formed only on the plane of the substrate.
However, the present inventors have found that the above-described stacked capacitor cell has the structural problem that, as the device becomes smaller, the capacitor capacity decreases, and it is therefore impossible to reduce the size of the device to a substantial extent, that is, it is impossible to form a memory circuit with a high integration density. This problem is attributable to the fact that, when the contact hole 312 is to be formed, it is necessary to take into consideration an alignment tolerance for etching between the contact hole 312 and the gate electrode 34 or the plate electrode 310 in order to prevent these electrodes from being partially exposed. Moreover, the conventional stacked capacitor cell needs to have a considerably large alignment tolerance for masks used to form the contact hole 312 and the gate electrode 34 or the plate electrode 310. This is because the mask used for the formation of the contact hole 312 which is carried out close to the end of the process needs to have a large tolerance in view of a worst case situation of a misalignment of the patterns which have already been exposed. More specifically, in the case of a mask which is only required to be aligned with a layer directly below it, it suffices to have an alignment tolerance which is needed in a single photoresist step, whereas, in the case of the contact portion of the stacked capacitor cell, it is necessary not only to align the mask with the diffusion layer under the layer which is to be etched, but also to have an alignment tolerance with respect to the gate electrode 34 or the plate 310 which may cause a short circuit if the mask should be misaligned. Accordingly, it is necessary to have an alignment tolerance corresponding to the sum of alignment tolerances which are required in a plurality of steps from the photoresist step for the diffusion layer to the photoresist step for the gate electrode or plate electrode. Moreover, it is also necessary to have an alignment tolerance in order to enable the plate electrode 310 to cover the lower electrode 38 completely. Thus, it is necessary to have large alignment tolerances for the two portions, and this limits the area of the lower electrode 38 of the capacitor, resulting in a reduction in the storage capacity.